The present invention relates to a phase change memory device and a method for manufacturing the same, and more particularly to a phase change memory device, which can decrease leakage current and increase a sensing margin and a method for manufacturing the same.
Memory devices are largely classified into a volatile RAM (random access memory) which loses inputted information when power is interrupted and a non-volatile ROM (read-only memory) which continuously maintains the stored state of the inputted information even when power is interrupted. The different types of a volatile RAM include a DRAM (dynamic RAM) and an SRAM (static RAM), and the different types of the non-volatile ROM include a flash memory device such as an EEPROM (electrically erasable and programmable ROM).
It is well known in the art that a DRAM is an excellent memory device, but a DRAM requires a high charge storing capacity, which in turn requires the surface area of an electrode to increase, such that a high level of integration very difficult to accomplish. Further, in a flash memory device, a higher operation voltage than a power source voltage is required due to the two gates stacked upon each other in a flash memory device, such that a separate booster circuit is needed to supply a voltage required for write and delete operations. All these factors present difficulties to accomplish a higher level of integration.
Under these situations, the so-called phase change memory device drew attention for search in an effort to develop a novel memory device having a simple configuration and capable of accomplishing a high level of integration while retaining the characteristics of the non-volatile memory device.
In a phase change memory device, a phase change from a crystalline state to an amorphous state occurs in a phase change layer interposed between a lower electrode and an upper electrode due to a current flow between the lower electrode and the upper electrode, and the information stored in a cell is recognized by utilizing the difference in resistance between the crystalline state and the amorphous state.
A chalcogenide layer being a compound layer made of germanium (Ge), stibium (Sb), and tellurium (Te) is used as a phase change layer in a phase change memory device. When a current is applied, heat is produced, i.e., the Joule heat, in the phase change layer, and the heat causes the phase change layer to change the phase between the amorphous state and the crystalline state. The resistance of a phase change layer in the amorphous state is higher than the resistance of the phase change layer in the crystalline state, as such whether the information stored in a phase change cell has a logic value of ‘1’ or ‘0’ can be determined by sensing the current flowing through the phase change layer in a read mode.
When manufacturing a phase change memory device over 512 Mb, vertical PN diodes were suggested in the art for use as the switching elements, as such the use of vertical PN diodes as the switching elements could allow the cell size to decrease less than 6 F2.
The vertical PN diodes are formed in the line-shaped N-type impurity regions formed in the active regions. Plugs contacting the electrodes that are electrically connected to the word lines are formed on the N-type impurity regions formed between the vertical PN diodes.
Among the electrodes electrically connected to the word lines, Vdd applied to the electrodes connected to the non-selected word lines is +1V in a read operation or +2V in a write operation. Zero voltage (0V) is applied to the electrodes electrically connected to the selected word lines.
However, there are problems in the conventional art in that, when the zero voltage is applied to the electrodes connected to the selected word lines, a voltage of up to 5V is consequently applied to the other electrodes adjoining the electrodes connected to the selected word lines. When the voltage difference between the electrodes increases up to 5V, this would lead to formation of NPN bipolar transistors, which in turn causes a leakage current to be produced along the lower boundary of the device isolation structure. Because this type of leakage current can exert influence on the current flowing from the vertical PN diodes to the electrodes connected to the selected word lines, it will affect the sensing margin of the phase change memory device to decrease.
One solution proposed for solving this problem suggests forming a device isolation structure to an increased depth so as to decrease the leakage current; however, this is not considered a plausible solution since it will inevitably increase the cell size, thereby decreasing the cell efficiency.